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AS1507 dual 256-tap digital potentiometer with spi interface and high endurance eeprom data sheet www.austriamicrosystems.com revision 1.00 1 - 17 1 general description the AS1507 is a linear, dual 256-tap digital potentiome- ter specifically designed to replace discrete/mechanical potentiometers and is ideal for applications requiring a low-temperature-coefficient variable resistor. the device is controlled vi a a 3-wire spi-compatible interface and features an internal eeprom for storing wiper positions. several device variants are available differentiated by end-to-end resistance as shown in ta b l e 1 (see also ordering information on page 16 ). the 3-wire spi-compatible serial interface allows com- munication at data rates up to 5mhz. the internal eeprom stores the last wiper position for initialization during power-up. the devices are available in an tqfn 3x3mm 16-pin package. figure 1. block diagram 2 key features high endurance: eeprom up to 10m cycles high reliability: eeprom up to 150 years data retention @ 85c wiper position retained in eeprom and loaded at power-up 256 tap positions 0.5lsb dnl in voltage divider mode 0.5lsb inl in voltage divider mode end-to-end resistance: 10/50/100k low end-to-end resistance temperature coefficient: 90ppm/oc low-power standby mode: 100na 5mhz spi-compatible serial interface single-supply operation: +2.7 to +5.5v tqfn 3x3mm 16-pin package 3 applications the device is ideal for mechanical potentiometer replacement, low-drift programmable gain amplifiers, audio volume control, lcd contrast control, and low-drift programmable filters. table 1. standard products model end-to-end resistance (k ) AS1507-10 10 AS1507-50 50 AS1507-100 100 256-position decoder 16-bit eeprom 8-bit latch spi interface 8-bit latch AS1507 256-position decoder 8 25 2 sclk 1 v dd 3 sdio 4 csn 13 low a 7 gnd 14 wiper 15 high a spi interface 8-bit latch 8-bit latch 256-position decoder 8 25 256-position decoder power- on reset 12 high b 11 wiper 10 low b 16 mute 9 ready
www.austriamicrosystems.com revision 1.00 2 - 17 AS1507 data sheet - pinout 4 pinout pin assignments figure 2. pin assignments (top view) pin descriptions table 2. pin descriptions pin number pin name description 1v dd 2.5 to 5.5v supply voltage. bypass with a 0.1f capacitor to gnd. 2sclk serial clock input 3sdio serial data input 4csn active-low chip select 5, 6, 8 nc not connected 7 gnd ground 9 ready eeprom ready. active-low indicates an ongoing write operation in the eeprom. 10 low b low terminal of resistor b. the voltage at this pin can be greater than or less than the voltage at pin high. current can flow into or out of this pin. 11 wiper b wiper terminal for resistor b 12 high b high terminal of resistor b. the voltage at this pin can be greater than or less than the voltage at pin low. current can flow into or out of this pin. 13 low a low terminal of resistor a. the voltage at this pin can be greater than or less than the voltage at pin high. current can flow into or out of this pin. 14 wiper a wiper terminal for resistor a 15 high a high terminal of resistor a. the voltage at this pin can be greater than or less than the voltage at pin low. current can flow into or out of this pin. 16 mute mute. both wiper registers are asynchronous ly set to zero. data stored in the eeprom is not affected. active-high signal. internal pull-down resistor. can be left unconnected if not used. n/a exposed pad the exposed pad is not internally connec ted. connect to gnd or leave floating. 3 sdio 2 sclk 1 v dd 10 low b 11 wiper b 12 high b AS1507 4 csn 16 mute 15 high a 14 wiper a 13 low a 5 nc 6 nc 7 gnd 8 nc 9 ready
www.austriamicrosystems.com revision 1.00 3 - 17 AS1507 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in electrical character- istics on page 4 is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units comments v dd to gnd -0.3 +7.0 v all other pins to gnd -0.3 v dd + 0.3 v maximum continuous current into pins high, wiper, and low AS1507-10 +1 ma AS1507-50 +1 AS1507-100 +1 electrostatic discharge 1 kv hbm mil-std. 883e 3015.7 methods latch-up 1 1. the maximum rating voltage must not be exceeded during latch-up test of the device. -100 100 ma jedec 78 thermal resistance ja 48 oc/w on pcb operating temperature range -40 +85 oc storage temperature range -60 +150 oc junction temperature +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020c ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn).
www.austriamicrosystems.com revision 1.00 4 - 17 AS1507 data sheet - electrical characteristics 6 electrical characteristics v dd = +2.7 to +5.5v, high = v dd , low = gnd, t amb = -40 to +85 o c. typ values are at v dd = +5.0v, t amb = +25 o c (unless otherwise specified). table 4. electrical characteristics symbol parameter condition min typ max unit power supply v dd 2.70 5.5 v i dd standby current digital inputs = v dd or gnd, t amb = +25oc 0.1 0.5 a i op operating current (cmos write) includes non-volatile write to memory 1 110 200 a dc performance (voltage divider mode) n resolution 256 taps inl integral linearity 2 AS1507-10 0.5 1 lsb AS1507-50 & -100 0.25 0.5 dnl differential non-linearity 2 AS1507-10 0.5 1 lsb AS1507-50 & -100 0.25 0.5 tc r end-to-end resistance temperature coefficient t amb = 0 to +85 o c 90 ppm/oc full scale error AS1507-10 2.5 4 lsb AS1507-50 1.5 2.5 AS1507-100 1.5 2.5 zero scale error AS1507-10 1 2 lsb AS1507-50 0.1 0.7 AS1507-100 0.1 0.7 dc performance (variable resistor mode) inl integral linearity 3 AS1507-10 1 2 lsb AS1507-50 & -100 @ 3v 0.6 1.5 AS1507-50 & -100 @ 5v 0.5 1 dnl differential non-linearity AS1507-10 0.5 1 lsb AS1507-50 & -100 0.5 1 dc performance (resistor characteristics) r w wiper resistance 4 v dd = 3v 200 v dd = 5v 120 c w wiper capacitance 15 pf r ee end-to-end resistance AS1507-10 7.5 10 12.5 k AS1507-50 37.5 50 62.5 AS1507-100 75 100 125 inputs and outputs wiper voltage range gnd- 0.3 v dd + 0.3 v high voltage range low voltage range v ih digital input high voltage 5 v dd = 3v 2.1 v v dd = 5v 2.4 v il digital input low voltage 5 v dd = 3v 0.6 v v dd = 5v 0.8 i leak digital input leakage current 200 500 na c in digital input capacitance 5 pf i cont continuous dac current 1000 a
www.austriamicrosystems.com revision 1.00 5 - 17 AS1507 data sheet - electrical characteristics timing characteristics v dd = +2.7 to +5.5v, high = v dd , low = gnd, t amb = -40 to +85 o c. typ values are at v dd = +5.0v, t amb = +25oc (unless otherwise specified). see figure 20 on page 9 . digital timing data is guaranteed by design and characteriza- tion, and is not production tested. dynamic characteristics wiper -3db bandwidth 6 AS1507-10 1200 khz AS1507-50 220 AS1507-100 120 t s wiper settling time 7 AS1507-10 1100 ns AS1507-50 1600 AS1507-100 2200 non-volatile memory reliability data retention 8 t amb = +85oc 150 years endurance 8 t amb = +25oc 10m write cycles t amb = +85oc 1m t busy write non-volatile register busy time 20 ms 1. the programming current operates only duri ng power-up and non-volatile memory writes. 2. dnl and inl are measured with the potentiometer configured as a voltage-divider with high = v dd and low = gnd. the wiper terminal is unloaded and meas ured with a high-input-impedance voltmeter. 3. dnl and inl are measured with the potentiometer configured as a variable resistor. high is unconnected and low = gnd. for the 5v condition, the wiper termina l is driven with a source current of 400a @ 10k , 80a @ 50k , 40a @ 100k . in 3v conditions, the wiper terminal is dr iven with a source current of 200a @ 10k , 40a @ 50k , 20a @ 100k . 4. the wiper resistance is measured using the source curre nts given in note 3. the number is the worst case resistance over tap positions. 5. the device draws higher supply current when the digital inputs are driven with voltages between (v dd - 0.5v) and (gnd + 0.5v). 6. wiper at midscale with a 10pf load (dc measurement) v dd = 5v, low = gnd. an ac source (5v peak to peak sinus signal) is applied to high and the wiper output is measured. a 3db bandwidth occurs when the ac wiper/high value is 3db lower than the dc wiper/high value. 7. wiper-settling time is the worst-case 0 to 50% rise-t ime measured between successive wiper positions. high = v dd , low = gnd; wiper is unloaded and measured with a 10pf load. 8. this parameter is not tested but ensured by characterization. table 5. timing characteristics symbol parameter condition min typ max unit f sclk sclk frequency 5 mhz t cp sclk clock period 200 ns t ch sclk pulse-width high 40 ns t cl80 sclk pulse-width low 40 ns t css csn-fall to sclk rise setup 40 ns t csh sclk-rise to csn-rise hold 40 ns t ds sdio to sclk setup 10 ns t dh sdio hold after sclk 0 ns t cs0 sclk-rise to csn-fall delay 40 ns t cs1 csn-rise to sclk-rise hold 40 ns t csw csn pulse-width high 200 ns t busy write non-volatile register busy time 20 ms table 4. electrical characteristics (continued) symbol parameter condition min typ max unit
www.austriamicrosystems.com revision 1.00 6 - 17 AS1507 data sheet - typical operating characteristics 7 typical operating characteristics v dd = 5v (unless otherwise specified). figure 3. dnl vs. tap position 10k , divider mode figure 4. inl vs. tap position 10k , divider mode figure 5. dnl vs. tap position 50k , divider mode figure 6. inl vs. tap position 50k , divider mode figure 7. dnl vs. tap position 100k , divider mode figure 8. inl vs. tap position 100k , divider mode -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap pos ition dnl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap position inl (lsb) . -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 tap pos ition inl (lsb) . -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 tap pos ition dnl (lsb) . -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 tap position inl (lsb) . -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 32 64 96 128 160 192 224 256 tap pos ition dnl (lsb) .
www.austriamicrosystems.com revision 1.00 7 - 17 AS1507 data sheet - typical operating characteristics figure 9. dnl vs. tap position 10k , varistor mode figure 10. inl vs. tap position 10k , varistor mode figure 11. dnl vs. tap position 50k , varistor mode figure 12. inl vs. tap position 50k , varistor mode figure 13. dnl vs. tap position 100k , varistor mode figure 14. inl vs. tap position 100k , varistor mode -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap pos ition dnl (lsb) . -2 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2 0 32 64 96 128 160 192 224 256 tap position inl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap pos ition inl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap pos ition dnl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap pos ition dnl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 32 64 96 128 160 192 224 256 tap position inl (lsb) .
www.austriamicrosystems.com revision 1.00 8 - 17 AS1507 data sheet - typical operating characteristics figure 15. wiper resistance vs. tap; 5v figure 16. wiper resistance vs. tap; 3v figure 17. dac resistor vs. temperature figure 18. gain vs. bandwidth figure 19. eeprom data retention vs. temperature 0 20 40 60 80 100 120 0 32 64 96 128 160 192 224 256 tap pos ition resistance ( ) . 0 20 40 60 80 100 120 140 160 180 0 32 64 96 128 160 192 224 256 tap position resistance ( ) . -12 -9 -6 -3 0 1 10 100 1000 10000 frequency (khz) gain (db) . 10k 50k 100k 110 111 112 113 114 115 116 117 118 25 35 45 55 65 75 85 temperature (c) resistance (k ) . 10 100 1000 10000 25 45 65 85 105 125 temperature (c) data retension (years) .
www.austriamicrosystems.com revision 1.00 9 - 17 AS1507 data sheet - detailed description 8 detailed description the AS1507 contains two resistor arrays with 255 resist ive elements each (tap points), and has a total end-to-end resistance of 10, 50, or 100k (see ordering information on page 16) . the device provides high, low, and wiper terminals for a st andard voltage-divider configur ation. pins high, low, and wiper can be connected in any configuration as long as their voltages fall between gnd and v dd . a 3-wire, spi-compatible serial interface controls move ment of the wiper among the 256 tap points. the eeprom stores the wiper positi on and recalls the stored wiper position upon powe r-up. the eeprom typica lly holds wiper data for 150 years and up to 10m wiper store cycles. analog circuit the 256 tap points are accessible to the wiper along the re sistor string between pins hi gh and low (similar to the end terminals of a mechanical potentiometer). the wiper tap point is selected by programming 8 data bits and a control byte via the 3-wire serial interface (see programming the device on page 10) . note: integrated power-on reset circuitry loads the wiper position from the eeprom at power-up. digital interface the AS1507 uses an spi-compatible 3-wire interface for comm and settings of the device consisting of two input sig- nals (chip-select - csn, and data clock - sclk) and one bi-d irectional data pin (sdio). driving csn low enables serial interface and the command/data are passed into the device synchronously by each sclk rising edge. there are 16-bit commands for write dat a into the wiper register or the non-volatile memory, and 8-bit commands for transferring data between wiper register and non-volatile me mory and to read the data stored in the wiper register or non-volatile memory. the 8-bit commands can be implemented in 16-bit command st ructure alternatively. in this case the first 8 bits shifted through the spi interface are not significant. the data byte passed at writing commands repre- sents the position of the wiper. after loading the 8- or 16-bit command while csn is low, t he loaded command is executed at the next rising edge of csn, simultaneously the serial interface is disabled. the csn signal must be low during the whole serial input stream through the spi, otherwise data on the spi interface are corrupted. note: if the data-in stream does not exactly contain 8 or 16 digits, no command is executed at the rising edge of csn. figure 20. serial data timing standby mode low-power standby mode is enabled at csn high. afte r a read access standby mode is entered 2 cycles of sclk after issuing the last bit of the data wiper or non-volatile register. if the digital inputs are stable v dd or gnd there is only leakage power dissipation of the device. this power dissipation is defined with 0.1ua (typ) at 25oc. t csh t cp t cs1 t csw t dh t ds t ch t cl t cs0 t css ... ... ... csn sclk sdio
www.austriamicrosystems.co m revision 1.00 10 - 17 AS1507 data sheet - detailed description eeprom (non-volatile register) there is an internal eeprom r egister implemented to retain the wiper position after power down. during an ongoing write cycle of the non- volatile register (t busy time) the system must not be po wered down. a write cycle on the eeprom is indicated by the ready signal. data retention defines the ab ility of an eeprom to retain data over time. the qualificat ion has been done according to jedec retention lifetime sp ecification (a117). the eeprom is cycled to the specified enduranc e limit before the data retention test is done. based on activation energy of 0. 6ev the data retention time derates over temperature as shown in figure 19 on page 8 . for the non-volatile register 1m endurance cycles and a data retention of 1 50 years are typical at 85 oc. the non-vola- tile register is factory trimmed to mid-scale. power-up the AS1507 contains an integrated power-up circuit. at powe r up, the data are transferr ed from the non-volatile mem- ory to the wiper register. the wiper register moves to the st ored position. this data transfer takes 5s after the supply has reached the por trigger level. programming the device write commands (see table 6) require 16 clock cycles (see figure 22 on page 12) to clock in the command and data. copy and read commands (see table 6) can use 8 clock cycles to clock in the command (see figure 21 on page 12) or 16 clock cycles. at 16 clock cycle commands the 8 data bits (d7:d0) are insignificant. table 6. command/data word format command 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 write wiper register a 0 0 0 0 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 write wiper register b 0 0 0 0 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write both wiper registers 0 0 0 0 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 write to non-volatile register a 0 0 0 1 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 write to non-volatile register b 0 0 0 1 0 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write to both non-volatile registers 0 0 0 1 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 copy wiper register a to non- volatile register 0 0 1 0 0 0 0 1 - - - - - - - - copy wiper register b to non- volatile register 0 0 1 0 0 0 1 0 - - - - - - - - copy both wiper registers to non-volatile registers 0 0 1 0 0 0 1 1 - - - - - - - - copy non-volatile register a to wiper register 0 0 1 1 0 0 0 1 - - - - - - - - copy non-volatile register b to wiper register 0 0 1 1 0 0 1 0 - - - - - - - - copy both non-volatile registers to wiper registers 0 0 1 1 0 0 1 1 - - - - - - - -
www.austriamicrosystems.co m revision 1.00 11 - 17 AS1507 data sheet - detailed description commands write wiper register this is a 16-bit command (see figure 22 on page 12) . the first byte represents the command word starting with the msb bit of the command, the second byte represents the dat a written to the wiper regist er (starting with the msb). data 0000 0000 the wiper moves the closest position to low, with data 1111 1111 the wiper moves to the closest posi- tion to high. the wiper registers can be written independentl y in two write cycles with different data or in one write cycle with the same data. note: at power-up the wiper position stored in the non-volatile memory are automatically loaded into the wiper regis- ter, the wiper moves to the related position. write to non-volatile register this is a 16-bit command (see figure 22 on page 12) . the first byte represents the command word starting with the msb bit of the command, the second byte represents the data written to the non-volatile memory. the wiper position is not changed by this command, since the wip er register is not affected. the non- volatile registers can be written inde- pendently in two write cycles wit h different data or in one wr ite cycle with the same data. there is a write non-volatile r egister time defined in the timing specification, which is requir ed for storing the data in the non-volatile register. the ready pin indicates the write time with an active-low signal. during this time the device must not be powered down, otherwise the data stor ed in the non-volatile register is corrupted. copy wiper register to non-volatile register this command can be implemented as an 8- or 16-bit comm and. the data stored in the wip er register are transferred to the non-volatile memory, to keep the data during power-dow n. there is no automatic trigger of this command during power-down of the device. this command must be triggered before powering down the device. there is a write non-volatile r egister time defined in the timing specification, which is requir ed for storing the data in the non-volatile register. during this time the device must not be powered down, otherwise the data stored in the non-vola- tile register is corrupted. copy non-volatile register to wiper register this command can be implemented as an 8- or 16-bit command. the data stored in the non-volatile register are trans- ferred to the wiper register, the wiper register moves to t he stored position. this command is automatically executed during power up of the system. read non-volatile register the AS1507 features the capability to read the data fr om the non-volatile register via the spi interface (see figure 23 on page 12) . this command can be implemented as an 8- or 16-bit command. the sdio pin is a bi-directional pin. during the csn low phase of the sequence the sdio pin is used as input pin to set the command byte. after csn ris- ing edge the pin sdio is set as output pin, the data stored in the non-volatile register are read serially, msb first. the data propagation starts at the second rising edge of sc lk after the rising edge of csn. csn must be high during the read operation. with the next falling edge of csn the sdio pin is set to an input pin again. read wiper register the AS1507 features the capability to read the dat a from the wiper register via the spi interface (see figure 23 on page 12) . this command can be implemented as an 8- or 16-bit co mmand. the sdio pin is a bi-directional pin. during the csn low phase of the sequence, the sdio pin is used as input pin to set the command byte. after csn rising edge the pin sdio is set as output pin, the data stored in the wiper register are read serially, msb first. the wiper position is unchanged. the data propagation starts at the second rising edge of sc lk after the rising edge of csn. csn must be high during the read operation. with the next falling edge of csn the sdio pin is set to an input pin again. mute command when a high signal is applied on the mute pin both wiper positions are set to zero permanently. while in mute opera- tion spi commands to wiper registers ar e not executed. data stored in non-volatile registers are not affected by the mute command. the mute pin includes a pull-down resistor. if a mute function is not required the pin can be left unconnected.
www.austriamicrosystems.co m revision 1.00 12 - 17 AS1507 data sheet - detailed description figure 21. 8-bit command word figure 22. 16-bit command/data word figure 23. 16-bit read command figure 24. 16-bit eeprom write command csn sclk sdio c7 c6 c5 c4 c3 c2 c1 c0 csn sclk d7 d6 d5 d4 d3 d2 d1 d0 sdio c7 c6 c5 c4 c3 c2 c1 c0 csn sclk d7 d6 d5 d4 d3 d2 d1 d0 sdio c7 c6 c5 c4 c3 c2 c1 c0 csn sclk d7 d6 d5 d4 d3 d2 d1 d0 sdio 0 00 10 0c1 c0 ready tbusy
www.austriamicrosystems.co m revision 1.00 13 - 17 AS1507 data sheet - application information 9 application information the AS1507 is intended for circuits requiring digitally contro lled adjustable resistance, such as lcd contrast control (where voltage biasing adjusts the display contrast), or programmable filters with adjus table gain and/or cutoff fre- quency. programmable filter figure 25 shows the configuration for a 1st-order programmable filter. the dc gain of the filter is adjusted by r 2 and can be calculated as: g = 1 + (r 1 /r 2 )(eq 1) the cutoff frequency (f c ) is adjusted by r 3 , and can be calculated as: f c = 1/(2 x r 3 x c) (eq 2) figure 25. programmable filter circuit offset voltage and gain adjustment connect one potentiometer of the AS1507 to an op amp to nu llify the offset voltage over the operating temperature range. use the second potentiometer in the fe edback path to adjust the gain of the op amp ( figure 26 ). figure 26. offset voltage and gain adjustment circuit + ? v in r 3 r 1 v out c in AS1507 higha lowa r 2 highb wiperb lowb wipera 5v AS1507 + ? higha lowa highb wiperb lowb wipera
www.austriamicrosystems.co m revision 1.00 14 - 17 AS1507 data sheet - application information positive lcd bias control the device can be used in applications where a voltage-divider or variable resistor is used to make an adjustable, pos- itive lcd-bias voltage, such as for the as1120 lcd driver. the op amp provides buffering and gain to the resistor- divider network made by the potentiometer ( figure 27 ) or to a fixed resistor and a variable resistor ( figure 28 ). figure 27. positive lcd bias control using a voltage divider figure 28. positive lcd bias control using a variable resistor adjustable voltage reference figure 29 shows the device used as the feedback resistor in an adjustable voltage-reference application. output volt- ages of external voltage references, supervisory reset th resholds, or led brightness control can be independently adjusted by changing the wi per position of the AS1507. figure 29. adjustable voltage reference circuit ? v out = 1.23v(50k /r 2 (k ) + ? 5v v out high wiper low 30v AS1507 + ? 5v v out high wiper low 30v AS1507 5v higha wipera lowa v in out adj v outref1 AS1507 highb wiperb lowb v in out adj v outref AS1507
www.austriamicrosystems.co m revision 1.00 15 - 17 AS1507 data sheet - pack age drawings and markings 10 package drawings and markings the device is available in an tqfn 3x3mm 16-pin package. figure 30. tqfn 3x3mm 16-pin package notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994 . 2. all dimensions are in millimeters, angle is in degrees. 3. n is the total number of terminals. 4. terminal #1 identifier and terminal numbering conventi on shall conform to jesd 95 -1 spp-012. details of ter- minal #1 identifier are optional, but must be located within the area indi cated. the terminal #1 identifier may be either a mold, embedded metal or mark feature. 5. dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. 6. nd refers to the maximum number of terminals on d side. 7. unilateral coplanarity zone applies to the ex posed heat sink slug as well as the terminals. symbol min typ max notes a 0.70 0.75 0.80 1, 2 a1 0.00 0.02 0.05 1, 2 l 0.30 0.40 0.50 1, 2 l1 0.03 0.15 1, 2 k0.20 1, 2 aaa0.101, 2 bbb0.101, 2 ccc 0.10 1, 2 ddd0.051, 2 symbol min typ max notes d bsc 3.00 1, 2 e bsc 3.00 1, 2 d2 1.55 1.70 1.80 1, 2 e2 1.55 1.70 1.80 1, 2 0o 14o 1, 2 b 0.18 0.25 0.30 1, 2, 5 e0.5 n161, 2 nd 4 1, 2, 5
www.austriamicrosystems.co m revision 1.00 16 - 17 AS1507 data sheet 11 ordering information the device is available as the standard products shown in table 7 . table 7. ordering information model marking description end-to-end resistance delivery form package AS1507-btdt-10 aspf dual 256-tap, non-volatile, spi digital potentiometer 10k tape and reel tqfn 3x3mm 16- pin AS1507-btdt-50 aspe dual 256-tap, non-volatile, spi digital potentiometer 50k tape and reel tqfn 3x3mm 16- pin AS1507-btdt-100 aspd dual 256-tap, non-volatile, spi digital potentiometer 100k tape and reel tqfn 3x3mm 16- pin
www.austriamicrosystems.co m revision 1.00 17 - 17 AS1507 data sheet - ordering information copyrights copyright ? 1997-200 7, austriamicrosystems ag, schloss premstaett en, 8141 unterpremstae tten, austria-europe. trademarks registered ?. all rights reserved. the materi al herein may not be reprodu ced, adapted, merged, trans- lated, stored, or used witho ut the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from pa tent infringement. austriami- crosystems ag reserves the right to chang e specifications and prices at any ti me and without notice . therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems ag for current information. this product is intended for use in normal commercial a pplications. applications requiring extended temperature range, unusual environmental requirements, or high reliability app lications, such as military, medical life-support or life- sustaining equipment are specifically not recommended wit hout additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or ar ising out of the furnishing, performance or use of the tech- nical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag a-8141 schloss premstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact

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